Leakage power reduction for reactive computation

Because of device scaling, leakage power is becoming a consistent fraction of the total power dissipated in CMOS circuits. In particular, it is dominant in reactive systems characterized by burst computations followed by long periods of inactivity. To reduce leakage power during such periods, we propose a new methodology that, di erently from existing techniques, does not require process or electrical level modi cations, but only the use of two additional power supplies.